A memory controller as a signal control circuit includes a DDR memory interface circuit represented, for example, by a double data rate three (DDR3). The DDR memory inputs and outputs data on both a positive edge and a negative edge of a clock signal, thus transferring data at a data transfer rate doubling a clock frequency.
In the DDR memory, the memory controller sends an internal clock signal generated therein to a dual inline memory module (DIMM).
In response to a read request from the memory controller, the DIMM generates a data strobe (DQS) signal from the clock signal and sends the DQS signal together with a data (DQ) signal to the memory interface.
The memory interface receives the DQS signal and the DQ signal. Next, based on phase information (edge) included in the received DQS signal, the memory interface determines optimum timing to capture the DQS signal. The memory controller then captures the DQ signal at the determined timing.
A delay that occurs midway in components through which the DQS signal and the DQ signal are sent, including the memory controller, a printed circuit board (PCB), and a memory device, varies depending on a device operating environment, such as temperature and power source voltage. This results timing at which the DQS signal or the DQ signal reaches the memory controller being varied according to changes in the device operating environment. A recent trend toward higher data transfer rates has been increasingly affecting variations in the delay. For this reason, a current practice is to determine optimum data capture timing by following the variations in the signal arriving timing.
Furthermore, a timing margin for reading the DQ signal is shrinking with the recent increasing trend toward higher-rate memory interfaces. Thus, desirably, accuracy in timing to read the DQ signal is improved.
Japanese Laid-open Patent Publication No. 2009-232366 discloses a technique that, in order to read data at appropriate timing, considers probabilities of occurrence of 0's and 1's and, based on phase shifts in, and rising and falling edges of, the data signal, adjusts a duty cycle.
Japanese Laid-open Patent Publication No. 2007-228044 discloses another technique that retains different delay amounts for rising and falling edges, respectively, of the signal, thereby assigning a different delay amount for each of the rising and falling edges.
The DQS signal may, however, be subject to duty deterioration in a level converter that converts an internal voltage of the memory controller into an external voltage or along a transmission path. The DDR memory captures the DQ signal on both the rising and falling edges of the DQS signal. If the duty deterioration occurs at this time in the DQS signal, a reduced timing margin in capturing the DQ signal results, so that a data failure may occur due to the DDR memory's failure to capture the DQ signal accurately.
Even with the use of the known technique of adjusting the duty cycle in consideration of the probabilities of occurrence of 0's and 1's, as disclosed in Japanese Laid-open Patent Publication No. 2009-232366, accurately capturing the data on the rising or falling edge of the DQS signal is difficult when the duty is deteriorated.
Similarly, even with the use of the known technique of assigning a different delay amount for each of the rising and falling edges to differentiate the delay amount of the rising edge from that of the falling edge, as disclosed in Japanese Laid-open Patent Publication No. 2007-228044, accurately capturing the data on the rising or falling edge of the DQS signal is difficult when the duty deterioration changes.